Timing Engineer (STA)

Mirafra Technologies
Sunnyvale, CA

Key Responsibilities:

  • Perform Static Timing Analysis (STA) for ASIC/SoC designs
  • Handle timing closure across multiple corners and modes
  • Work on timing sign-off using industry tools
  • Analyze and debug timing violations (setup/hold, noise, crosstalk)
  • Collaborate with design, physical design, and verification teams
  • Support ECO implementation for timing fixes

Required Skills:

  • Strong knowledge of timing concepts and constraints
  • Experience with tools like Synopsys PrimeTime, Tempus (Cadence)
  • Hands-on experience in SDC constraints, timing reports, and closure
  • Understanding of clock tree synthesis (CTS) and physical design flow
  • Familiarity with advanced nodes (7nm/5nm is a plus)

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