Application Specific Integrated Circuit Engineer

Requirement Details:

Job Title: ASIC Design Engineer – RTL / STA

Location: Santa Clara, CA

Experience: 5–6+ Years Required

Client: AMD

W2 on contract

Top 3 Skills:

• Strong understanding of SystemVerilog and RTL design
• Experience analyzing and modifying existing ASIC/SoC designs
• Familiarity with ASIC tools such as Lint, CDC, STA
• (Scripting experience in Perl/Python/Tcl is a nice-to-have)

Key Responsibilities:

• Write micro-architecture documentation and own major design/implementation of logic blocks to meet functional, timing, area, and power targets
• Collaborate with architecture and hardware teams to understand system-level requirements
• Work closely with verification and physical design teams to ensure high-quality design and successful tape-out
• Design logic for efficient test and debug
• Participate in post-silicon bring-up for owned features
• Contribute to cross-functional teams to address novel design challenges
• Drive automation initiatives to improve team productivity

Required Experience:

• 5–6+ years of ASIC/SoC RTL design experience
• Track record of successful production tape-outs
• Strong experience in designing RTL blocks for SoCs
• Proven expertise in IP integration
• Proficient with synthesis, STA, and timing optimization