We are hiring a Senior ASIC Design Engineer (RTL / SoC Block Owner) for a leading company in the semiconductor industry. This is a high-impact role focused on block-level micro-architecture, RTL design, and SoC integration for advanced silicon programs.
This position requires deep hands-on RTL development experience and ownership of complex digital blocks through the full ASIC lifecycle.
Location:
Austin, TX (On-site)
Duration:
12 Months Contract (Strong possibility of extension)
Employment Type:
W2 Only - No C2C or 1099. No third-party inquiries.
Key Responsibilities
- Own micro-architecture definition and RTL implementation for complex SoC blocks
- Develop synthesizable RTL using Verilog/SystemVerilog
- Drive block-level integration into large-scale SoCs
- Collaborate with verification, physical design, and architecture teams
- Support lint, CDC, RDC, and low-power checks
- Work with synthesis and STA teams to achieve timing closure
- Debug design issues across simulation and silicon bring-up
Required Qualifications
- 7+ years of ASIC RTL design experience
- Strong experience in Verilog and/or SystemVerilog
- Proven experience owning and delivering production silicon blocks
- Strong understanding of SoC architecture and digital design fundamentals
- Experience with synthesis and timing analysis flows
- Familiarity with industry tools (Design Compiler, PrimeTime, VCS, etc.)
- Experience working on high-performance or low-power designs
Preferred Experience
- CPU, GPU, NPU, or high-speed datapath design experience
- Cache, memory subsystem, or interconnect design
- Low-power design methodologies (clock gating, power domains)
- Experience supporting silicon bring-up
This is an excellent opportunity to work on cutting-edge semiconductor technology with a high-visibility engineering team.
