Technical Lead Product Engineer
San Jose, California, United State
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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.co
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Job Descripti
on:
We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objecti
ves.
Basic Qualificat
- ions:Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or valida
- tion)Experience in working with PCIe Gen3 and
- aboveHave gone through at least one cycle of full product development life
- cycleStrong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS pref
- erredStrong problem-solving skills that involve system level analysis with test hardware, test program and
- DUT.Digital and analog circuit level understanding for
- DUT.Excellent team player with great communication s
- killsProfessional attitude with the ability to prioritize a dynamic list of multiple
tasks
Required Exper
- ience:
Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test so - lutionsHands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)
- DDR5/4.Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consiste
- nt BKMsStrong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conc
- lusionsEnergetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of deve
lopment
Preferred Exp
- erience:
Working with silicon validation teams to ensure device performance meets production requ - irements.Firmware development in C/C++, scripting in Python, or other equivalent programming ex
- perience.Hands on experience in product/package qual
ification