Description
Key Responsibilities - Perform PDK installation, configuration, and validation for multiple technology nodes (Samsung Foundry 4nm, 2nm etc.) - Flow set up and design environment maintenance, primarily o Cadence Virtuoso o CalibreDRC, CalibreLVS o Cadence EMX, Quantus - Perform Top layout and sub-cells o Interpret and debug layout issues
Requirements
Preferred Skills - At least 7 years of experience of direct experience in CAD engineering and advanced node tapeout - Verification using Cadence Quantus/QuantusFS or CalibrexRC/xACT/xACT3D for BEOL, VIAs, transistor level as well as Cell level flows. - Knowledge of CalibreLVS, CalibreDRC decks and flow is preferred - Understanding of 3D Field Solver tools such as Cadence EMX or Ansys HFSS. - Understanding of Semiconductor Technology and Process, Semiconductor Device Physics, process modelling, and mask layouts - Understanding of BEOL/FEOL process architecture for technologies such as planar, FD-SOI, FinFETs and GAE, etc will be a plus. - Experience with Samsung Foundry is a plus - Attention to details, exceptional focus on understanding the problems at hand and ensure thoroughness in problem-solving - Good written and verbal communication skills, with outstanding teamwork capabilities - Self-motivated with a growth mindset - MS in Electrical Engineering, Physics, related field or equivalent work experience;