Staff Physical Design Engineer – Top-Level Clock Distribution

We are seeking a Senior/Staff Physical Design Engineer with deep expertise in top-level clock architecture and CTS implementation for advanced-node SoCs (5nm / 3nm / 2nm).

The ideal candidate will have strong experience designing large-scale clock distribution networks including H-Tree, Mesh, and Hybrid architectures while driving ultra-low skew clock signoff.

You will collaborate with Physical Design, STA, RTL, and Power teams to ensure robust clock quality and tapeout readiness.

Key Responsibilities

• Design and optimize top-level clock distribution architectures.
• Implement and analyze:
• H-Tree
• Clock Mesh
• Hybrid Clock Structures
• Drive CTS for low skew and balanced latency.
• Optimize clock power using advanced gating techniques.
• Validate clock signal integrity and duty cycle distortion (DCD).
• Debug large-scale clocking issues across full-chip integration.
• Collaborate with STA and PD teams for clock-timing convergence.
• Develop scalable methodologies for clock signoff closure.
• Ensure robust clock quality at advanced nodes and large die scale.

Required Technical Skills

Clocking / CTS

• Clock Tree Synthesis (CTS)
• H-Tree Architecture
• Clock Mesh
• Hybrid Clock Structures
• Duty Cycle Distortion (DCD)
• Clock Skew Optimization
• Clock Power Optimization

Tools

• Cadence Innovus
• Synopsys Fusion Compiler
• Specialized CTS Engines

Preferred Plus

• SPICE simulation expertise

Advanced Nodes

• 5nm
• 3nm
• 2nm

Scripting

• Tcl
• Python
• Perl