Field-Programmable Gate Arrays Engineer

FPGA Engineer – HAPS & ZeBu Prototyping

Key Requirements:

• Strong experience in FPGA prototyping platforms like Synopsys HAPS and Synopsys ZeBu
• Hands-on with RTL design/verification (Verilog/SystemVerilog)
• Experience in FPGA bring-up, debugging, and validation
• Knowledge of partitioning large SoC designs across multiple FPGAs
• Familiarity with clocking, reset strategies, and timing closure
• Experience with high-speed interfaces (PCIe, Ethernet, DDR, AXI)
• Strong debugging skills using logic analyzers, waveform tools, and emulation debug flows

Nice to Have:

• Experience with UVM-based verification
• Exposure to SoC architecture and CPU subsystems
• Scripting in Python/TCL

Responsibilities:

• Develop and maintain FPGA prototypes using HAPS/ZeBu
• Perform design partitioning, synthesis, and timing optimization
• Debug issues across RTL, FPGA, and emulation environments
• Collaborate with design and validation teams for pre-silicon verification
• Enable software bring-up on emulation/prototyping platforms