Job Title: DFT DV Engineer
Location: Santa Clara, CA
Onsite/ Remote: Onsite
Visa: USC/GC/H1b
Duration: 12 Months
Required Skills:
Experience in Scan insertion with compression for Stuck-At and At-Speed test.
Experience in Scan ATPG (Stuck-At and At-Speed), coverage analysis, simulation and debug
Experience in MBIST insertion, simulation and debug on RTL and gates netlist
Experience in Boundary Scan insertion, simulation and verification.
Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys)
Good written and verbal communication skills in English
STA DFT Test mode timing constraint development and analysis is a plus
Knowledge of Verilog HDL and experience with simulators and waveform debugging tools
Experience with ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data a plus.