ASIC/FPGA Verification Engineer (UVM/SystemVerilog)

Job Title: ASIC/FPGA Verification Engineer (UVM/SystemVerilog)

Location: Mountain View, CA (100% Onsite)

Duration: 12 Months Contract

Pay Rate: $84 – $85/hr

Job Summary

We are seeking an experienced ASIC/FPGA Verification Engineer to support development of advanced microelectronics for space, avionics, and defense applications. This role focuses on verifying complex ASIC and FPGA designs using SystemVerilog and UVM methodologies.

Key Responsibilities

• Develop and execute SystemVerilog/UVM-based testbenches
• Build reusable verification components (drivers, monitors, scoreboards)
• Perform functional and code coverage analysis
• Run simulations, CDC checks, and gate-level regressions
• Support FPGA bring-up, prototyping, and hardware integration
• Collaborate with cross-functional engineering teams

Required Qualifications

• Bachelor’s degree in EE, CE, CS, or related field
• Strong experience with SystemVerilog and UVM
• Experience in ASIC/FPGA verification and testbench development
• Familiarity with Linux and scripting (Python/Perl)

Preferred Qualifications

• 5+ years of verification experience
• Experience with FPGA prototyping and hardware emulation
• Knowledge of high-speed interfaces (PCIe, Ethernet, JESD204C)
• Experience with SVA and RTL design flows