Our client is a globally recognized leader in memory interface and digital control technologies, with a strong presence in data center, cloud computing, and communications markets. This is a great organization, known for its innovative culture, advanced engineering capabilities, and collaborative teams focused on delivering cutting-edge silicon solutions. They’re seeking a Senior Digital Design Engineer with 5+ years of experience to architect and develop RTL for a range of products. This role focuses on digital control systems (PMIC’s) as well as clock buffers and synchronizers. The ideal candidate will have hands-on experience with the full RTL-to-GDSII flow using industry-standard tools. Familiarity with embedded microcontrollers (such as RISC-V) and communication protocols like I2C, I3C, and SMBus is a plus. In this role, you will collaborate with global teams to design both individual building blocks and complete product solutions.
Key Responsibilities
Contribute as an individual designer within a collaborative, team-oriented environment
Design and implement logic and state machines using SystemVerilog/Verilog RTL
Develop, debug, and validate RTL using industry-standard simulation, synthesis, and analysis tools (including LEC, CDC/RDC, lint, DFT, and STA)
