Senior Design Verification Engineer

I'm working with a frontier AI lab building something genuinely different.

They're training AI models to design chips. Not co pilots for chip designers. The AI does the architecture, generates the RTL, and runs verification.

Founding team out of Anthropic, Google DeepMind, Meta, xAI, Apple and Intel. $20M+ seed. Already taping out on TSMC, Samsung and GF with industry partners, plus building their own inference platform in-house.

They're hiring three founding-tier DV engineers to own verification across real silicon programs and to shape how their AI-driven flow does verification at scale.

What you'd own:

• Verification strategy across internal and external SoC programs
• Sign-off across CPU subsystems, memory controllers, NoC, NPU and security IPs
• Building scalable simulation, emulation and FPGA collateral
• Working directly with the ML and agentic team to encode DV best practice into the AI flow
• Leading the DV function as the team scales from 14 to 35 this year

What they're looking for:

• 5 to 15 years tape-out experience at top chip companies or fast-moving silicon startups
• Deep UVM testbench architecture, built from scratch
• Strong SystemVerilog, virtual sequences, scoreboards, interface VIP, master/slave agents
• Subsystem depth in at least one of: CPU, memory controller, NoC, NPU/ML accelerator, security

If you've built UVM testbenches from scratch on real silicon and you want to be at the front of where chip design is going, message me and click apply.