Principal Design Verification Engineer

Jobs onsemi
Bengaluru, IN

 

Senior Principal Digital IC Verification Engineer - Digital Compute Team 

 

 

About Us 

 

 

At onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets. 

 

 

The Role 

 

 

We are expanding the team to India and are looking for a Senior Principal Digital IC Verification Engineer. You will participate to the development of embedded MCU and DSP systems as well as hardware accelerators for cryptography. 

 

 

Why Join Us 

 

 

We create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. We offer a competitive benefit package and a great place to work. You will be able to build up a career in a successful international company, and you can participate in interesting international projects. 

 

#LI-RT1

 

 

What You’ll Do

  • Define the verification strategy and the detailed verification plans for blocks and systems
  • Coordinate/lead the verification activities in the project teams and reach verification closure for the projects
  • Develop SystemVerilog/UVM environments for blocks and top-level SoCs
  • Debug functional errors in RTL
  • Participate to verification methodology improvement activities
  • Coach and mentor younger engineers

What You’ll Need

  • Minimum BS/MS in Electrical Engineering or related technical field
  • At least 13 years of digital verification experience
  • Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage
  • In-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion-based verification, test environment architecture & creation, regression management, coverage collection, and formal verification
  • #LI-RT1
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