Design Verification Engineer

ACL Digital
San Diego, CA

Top 5 Required Skills

  1. HVL Methodology: SystemVerilog/UVM.
  2. Simulation/Formal Tools: VCS, Xcellium/NCsim, Questa, VCFormal, Jaspergold.
  3. Protocols: High-speed Serdes interfaces (PCIe, USB3/4, UFS, MIPI CSI/DSI/HDMI, DDR PHY).
  4. Advanced Simulations (Plus): UPF-based power-aware simulations & Gate Level Simulations (GLS).
  5. Assertions/Debug: SystemVerilog Assertions (SVA), checkers, strong debugging.


Technologies

  • Protocols: PCIe, USB, MIPI, LPDDR, CXL, C2C, D2D, UFS.
  • Analog Blocks: PLL, DAC, ADC, Sensors.


Minimum Qualifications

  • Education: Master’s or Bachelor’s in EE, CE, or related.
  • Experience: 5+ years in ASIC design verification or related.


Pay Rate: $70/hr - $80/hr

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