Design Verification Engineer

Position: Design Verification Engineer

Location: San Diego, CA

Duration: 12 Months (High Possibility of Extension)

Job Description:

• Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.
• Knowledge of a HVL methodology like SystemVerilog/UVM.
• Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.
• Protocol knowledge of High Speed Serdes external interfaces like PCIe, USB3/4, UFS, MIPI CSI/DSI/HDMI and DDR PHY
• Good at implementing system Verilog assertions and checkers, good debugging skills
• Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.
• Experience in scripting languages (Python, or Perl).