Role: ASIC Design Engineer
Location: San Diego, CA (Onsite)
Type: Contract
Duration: Long Term
Rate: $54/hr -$58/hr on W2
- The client is looking for ASIC engineers who will be responsible performing SoC level low power implementation working as part of the team.
- The person will require to validate SoC power intent spec using in house native tool (UPF generation) and use Cadence Conforml Low Power validation tool.
- Task includes defining low power requirements implementation of digital, mixed-signal circuits and systems that are integrated into System-on-Chip (SoC).
- As part of the SoC power team the you will be interfacing with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development.
Best Regards,
Rupesh Kumar
Lead –Team Talent Acquisition
ALTEN Calsoft Labs
2890 Zanker Road, Suite 200, San Jose, CA 95134
D : +1 408-755-3056
E: rupesh.k@acldigital.com
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